The present invention relates to a structure and a manufacturing method of a semiconductor device composed of 1T1Cs (one transistor one capacitor), in particular, in which the surface area of a memory cell capacitor part is expanded in order to increase capacitance per bit, and also manufacturing efficiency is not made to decrease.
Recently, at a semiconductor device such as a DRAM, a stacked capacitor type memory cell structure, in which a memory cell capacitor part is stacked up, has been used. Generally, capacitance of a memory cell is in proportion to the surface area of the memory cell capacitor part, and is inverse proportion to the thickness of the dielectric film. Therefore, in order to increase the capacitance of the memory cell, it is desirable to expand the surface area of the memory cell capacitor part.
On the other hand, the size of the memory cell has been largely reduced corresponding to large scale integration of a DRAM. Consequently, at a capacitor forming region, its plane occupying area has been also reduced. For example, at a semiconductor device, whose line width is less than 0.28 xcexcm, manufactured by a micro process, the occupying area of the memory cell capacitor part is very narrow. As a result, the capacitance of the memory cell is decreased and the deterioration of the electric charge hold characteristic is generated. Therefore, in a technical trend that the semiconductor device is manufactured by a further micro process, a method, in which the capacitance of the memory cell is increased efficiently, has been required.
Referring to drawings, a conventional manufacturing method of a semiconductor device is explained. In the drawings, in order to make the explanation concise, manufacturing processes are divided into a few processes expediently. FIG. 1 is a diagram showing a first process at the conventional manufacturing method of the semiconductor device. As shown in FIG. 1, at the semiconductor device composed of the 1T1Cs, an impurity diffusion layer 11, in which a source and a drain of a transistor are formed, is formed on the surface of a semiconductor substrate (not shown). On this impurity diffusion layer 11, an interlayer 12 and an interlayer 13 being different from the interlayer 12 are formed. An anisotropic dry etching is applied to the interlayer 12 and the interlayer 13 by using resist as a mask, and a contact hole reaching to the impurity diffusion layer 11 is formed. After this, the contact hole is filled with a conductive layer 14 (DOPOS or Poly-Si) and the conductive layer 14 is formed on the interlayer 13.
FIG. 2 is a diagram showing a second process at the conventional manufacturing method of the semiconductor device. As shown in FIG. 2, the anisotropic dry etching is applied to the conductive layer 14 by using resist 16 as a mask, and a lower electrode of a memory cell capacitor part is formed. FIG. 3 is a diagram showing a third process at the conventional manufacturing method of the semiconductor device. A final completed shape of the lower electrode of the memory cell capacitor part is shown in FIG. 3. And a rectangular solid pattern at a cross sectional view separating each of memory cell capacitor parts is formed by the conductive layer 14 by applying the anisotropic dry etching.
The amount of electric charge storing in a memory cell capacitor part by data writing of one bit is proportion to the surface area of the conductive layer 14 (DOPOS or Poly-Si) on the interlayer 13 shown in FIG. 3. In order to increase the capacitance, the surface area of the conductive layer 14 is required to be as large as possible. In order to from a memory cell capacitor part whose surface area is expanded, a photo lithography process will be applied additionally. However, in case that this photo lithography process is added to the manufacturing processes of the semiconductor device, this manufacturing processes are made to be inefficient.
It is therefore an object of the present invention to provide a structure and a manufacturing method of a semiconductor device composed of 1T1Cs, in which the surface area of a memory cell capacitor part is expanded by forming an uneven surface on the surface of a lower electrode of the memory cell capacitor part in order to increase the capacitance of the memory cell per bit. And further, at manufacturing processes, a photo lithography process is not additionally required to manufacture the semiconductor device at the process that the lower electrode having the uneven surface is formed, therefore the manufacturing efficiency is not decreased.
According to a first aspect of the present invention for achieving the object mentioned above, there is provided a manufacturing method of a semiconductor device, in which at least a conductive layer is formed on an impurity diffusion layer in which a source and a drain of at least one transistor are formed, and a lower electrode of a memory cell capacitor part of a stacked capacitor type memory cell composed of 1T1C (one transistor one capacitor) is formed by removing a part of the conductive layer. The manufacturing method provides the steps of, forming a first insulation film on the conductive layer, applying a first etching for removing a part of the first insulation film and a part of the conductive layer to its middle part, and forming spaces being different sizes, forming a second insulation film on the whole surface formed by mentioned above steps so that a small size space of the spaces is filled with the second insulation film, applying an etching back for forming an exposed part of the conductive layer at a large size space of the spaces, and applying a second etching for removing the conductive layer at the exposed part of the conductive layer.
According to a second aspect of the present invention, in the first aspect, the conductive layer is made of Poly-Si, and the second etching is an anisotropic Poly-Si dry etching.
According to a third aspect of the present invention, in the first aspect, the first insulation film and the second insulation film are formed by an oxide film, the etching back is executed by an anisotropic oxide film dry etching, at the large space, the exposed part of the conductive layer is formed by that side walls of the oxide film are formed on side surfaces of the large space, and at the small space, a side wall of the oxide film is formed on a side surface of the small space, but the width of the side wall at the small space is almost equal to the width of the side wall at the large space, and the size of the small space is smaller than that of the large space, therefore the small space is completely filled with the side wall formed by the oxide film.
According to a fourth aspect of the present invention, in the first aspect, at forming the second insulation film, the thickness of the second insulation film is a half size of the horizontal direction size of the small space.
According to a fifth aspect of the present invention, in the first aspect, the first etching step provides a photo lithography process, and based on a resist pattern having different widths transferred on the upper surface of the first insulation film by the photo lithography process, a part of the first insulation film and a part of the conductive layer to its middle part are removed, and the spaces being different sizes are formed.
According to a sixth aspect of the present invention, in the first aspect, a manufacturing method of a semiconductor device further provides the step of, applying a third etching for removing remaining the first and second insulation films being oxide films by an oxide film wet etching after the second etching step.
According to a seventh aspect of the present invention, there is provided a structure of a semiconductor device, in which at least a conductive layer is formed on an impurity diffusion layer in which a source and a drain of at least one transistor are formed, and a lower electrode of a memory cell capacitor part of a stacked capacitor type memory cell composed of 1T1C (one transistor one capacitor) is formed by removing a part of the conductive layer. At the structure of the semiconductor device, the lower electrode provides two kinds of spaces at the conductive layer. And one of the two kinds of spaces is a small space and is disposed at the center part in the conductive layer, and the other of the two kinds of spaces is a large space and is disposed at the outer part in the conductive layer in a state that side surfaces of the large space have a difference in level at its middle part and the bottom surface of the large space reaches to an interlayer. Therefore, the surface of the lower electrode has an uneven surface by the structure mentioned above.